In a nonvolatile semiconductor memory device such as a NAND flash memory, downscaling and multi-valuing of memory cells are developed. When both memory cells are downscaled and memory cells store multi-valued data or either memory cells are downscaled or memory cells store multi-valued data, the number of kinds of voltages applied to word lines at a data write time increases to three or more. For example, conventionally, at a data write time, mutually different voltages are also applied to selected word lines and unselected word lines, respectively. However, in recent years, it is also considered to make a voltage of an unselected word line close to a selected word line and a voltage of an unselected word line separated from a selected word line different from each other. Further, it is also considered to make a voltage of an unselected word line at a side nearer to a source than to a selected word line and a voltage of an unselected word line at a side nearer to a bit line than to a selected word line different from each other. Therefore, the number of kinds of voltages applied to word lines increases to three or more.
When the number of kinds of voltages applied to word lines increases as described above, the number of word lines to which voltages are applied varies depending on a position of a selected word line. Varying the number of word lines to which voltages are applied means that a word line capacitance boosting to each voltage changes. Therefore, the time required for a charge pump to boost a voltage of a word line to each voltage varies depending on a write address. When a rise time of word lines varies in each write operation, electric properties (a threshold voltage, for example) of memory cells after a writing change depending on addresses. Fluctuations of electric properties of memory cells become disadvantageous particularly for multi-valued memory cells.
Further, when a drive capacity of a charge pump matches a maximum capacitance of a word line for each voltage, there is a risk that a voltage of the word line oscillates when a load of the charge pump is a minimum capacitance of the word line. This risk occurs because the charge pump cannot converge the voltage of the word line to a constant voltage when a boost capacity (a current drive capacity) of the charge pump is larger than a capacitance (a load) of the word line.
Furthermore, when a drive capacity of a charge pump is matched with a maximum capacitance of a word line for each voltage, a layout area of the charge pump becomes larger, and this is disadvantageous to downscaling of memory chips.